A network switch creates a network among a plurality of nodes (connected to personal computers, workstations, etc.) and other network switches connected thereto. As shown in FIG. 1 to which reference is now made, each node 10 is connected to one port of a switch 12. Further ports 14 also serve to connect network switches together. The switches are typically connected together via a bus 16. Optionally, a central processing unit (CPU) 15 which is associated with a main memory element 17 can also be connected to the bus 16. The CPU 15 overseas the communication operations which occur between the network switches 12. The main memory 17 temporarily stores packets of data to be transferred between switches 12.
Each node 10 sends packets of data to the network switch 12 which then routes the packets either to another of the nodes connected thereto or to a network switch to which the destination node is connected. In the latter case, the destination network switch then routes the packet to the destination node.
Each network switch also has to temporarily store the packets of data, in buffers 18, while the switch determines how, when and through which port to retransmit the packets. Each packet can be transmitted to only one destination address (a “unicast” packet) or to more than one unit (a “multicast” or “broadcast” packet). For multicast and broadcast packets, the switch typically stores the packet only once and transmits multiple copies of the packet to some (multicast) or all (broadcast) of its ports. Once the packet has been transmitted to all of its destinations, it can be removed from its buffer 18 or written over.
One example of a prior art process of transferring packets between network switches is illustrated in FIGS. 2A and 2B to which reference is additionally made. FIG. 2A is a block diagram illustration of the flow of data between the source and destination network switches and FIG. 2B is a timing diagram of the activity of the bus 16.
The source network switch 12A, on its own schedule reads the packet from its temporary storage location, labeled 19A, and writes the packet to the main memory 17 (step 20). The source network switch 12A then provides (step 22) an indication to the CPU 15 that the transfer has finished. At some later point after the transfer has finished, the CPU 15 indicates (step 24) to the destination network switch 12B that the main memory 17 is storing its data.
When the destination network switch 12B receives the notification from the CPU 15, the destination network switch 12B begins the read process and takes control of the bus 16. The read process includes steps 26-32, as follows. In step 26, the destination network switch 12B determines where, in its temporary storage unit there is room for the incoming packet (for example location 19B). In step 28, destination network switch 12B asks the main memory 17 to read the packet and, when the packet is received, switch 12B places it (step 30) into the available location 19B. When the destination network switch 12B has finished the read operation, it, in step 32, sends a message to the CPU 15 that the packet was properly received. In step 34, the CPU 15 receives the receipt message and clears the location in the main memory 17 in which the data was previously stored.
FIG. 2B illustrates the timing of the packet transfer. The packet transfer begins with the “source write” (SW) operation of steps 20-22 which is generally a short operation. At some later point, the destination read (DR) operation occurs. Since the read process includes allocating the storage location and accessing the main memory 17, and since main memory 17 typically reads at a slow rate, the read operation takes a long time. Unfortunately, during the read operation, no other switch can access the bus. Thus, the rate of data transfer is limited by the speed at which the main memory 17 can read the data, even if the bus 16 and the other components can operate at faster speeds.